1. Field of the Invention
The present invention relates to data writing into a memory cell in a semiconductor integrated circuit device. More particularly, the present invention relates to reduction of noise caused by a writing operation.
2. Description of the Related Art
With advancement of recent computer technology, as in depicting of a three-dimensional moving picture, there has been a need for a memory applicable to graphics use in which an address cycle irregularly changes. As a result, a high speed random access performance is required irrespective of a data readout cycle or a write cycle. However, as in a dynamic random access memory (hereinafter, referred to as a DRAM) or a synchronous type semiconductor memory device represented by a synchronous DRAM (hereinafter, referred to as a SDRAM), in a memory of such type multiplexing row addresses and column addresses, thereby inputting them at a separate timing, a high speed random access performance of such type cannot be achieved.
Because of this, as a high speed memory achieving a high cycle time performance of a static random access memory (hereinafter, referred to as a SRAM) while utilizing high integrity of DRAM or SDRAM, there has been devised a memory that determines a readout cycle or a write cycle by inputting addresses without multiplexing them, and by one command signal. A fast cycle random access memory (FC RAM (registered trademark)) is obtained as a typical device.
A memory cell section 1000 shown in FIG. 20 is a specific example showing a configuration of a high speed memory. Required constituent elements are excerpted for the purpose of explanatory convenience, and part of the high speed memory is shown. Memory cells Ta to Td are connected to bit lines /BL1, /BL2, BL1, and BL2. The data stored in the memory cell Ta to Td is read out as a stored charge, and the read data is redistributed into the bit lines /BL1, /BL2, BL1, or BL2. Then, bit line pair BL1 and /BL1 and bit line pair BL2 and /BL2 are paired, and the data are amplified by means of sense amplifiers SA and SAM. The amplified data is posted to data buses DB and /DB via a pair of column switches TN1 and TN2 and a pair of column switches TN3 and TN4, and amplified by means of read amplifier RA to output (Dout). Conversely, input data Din is amplified by means of a write amplifier WA, and the amplified data is stored by being stored as a charge in the memory cells Ta to Td from the data buses DB and /DB via bit lines BL1 , /BL2, BL1, or BL2.
Selection of the memory cells Ta to Td to be connected to the bit lines /BL1, /BL2, BL1, or BL2 is as follows. First, a row control circuit RC receives an internal command signal CMD generated in accordance with a readout or write cycle determined by an external one command signal (not shown), and an active signal ACT and a precharge signal PRE are output. Of these signals, these sent to a word decoder WD activates or deactivates the word decoder WD, and initiates word lines WL and WLM. In addition, those input to a sense amplifier signal circuit SC activates the same amplifiers SA and SAM to control an activation signal LE.
Apart from the shown memory cells Ta and Td, a number of memory cells (not shown) are connected to bit lines BL1 and /BL1 or the like, and these memory cells are sequentially selected by means of a word line (not shown) selected by the word decoder WD based on the row address signals ADRn (n=1, 2, . . . ). Therefore, it is required to short bit line pair BL1 and /BL1 or the like every memory cell access, and precharge these pairs at a predetermined voltage (VPR). This precharge operation is carried out by bit line short circuits BS and BSM. The bit line short circuits BS and BSM are controlled by a bit line short signal BRS from a bit line short signal circuit BSS based on the active signal ACT and the precharge signal PRE from the row control circuit RC.
In addition, the column switch signal circuits CS and CSM receive control signals WC and WCD output from a column control circuit CC based on an internal command signal CMD and a column address signals ADCn (n=1, 2, . . . ), and outputs switch signals CL1 and CL2 as required according to the column address signals ADCn (n=1, 2, . . . ). In this manner, the column switch TN1 to TN4 are conductive or nonconductive.
It is required to short and precharge the data buses DB and /DB by every readout or write cycle as in the bit line pair BL1 and /BL1 or the like. This precharge operation is carried out by a data bus short circuit DBS. The data bus short circuit DBS is controlled by a data bus short signal CPR from a data bus short signal circuit DBSS based on the control signals WR and WCD from the column control circuit CC.
FIG. 21 is a time chart showing a write operation for a memory cell section 1000 of the prior art. At a time t0, an internal command signal CMD is output, a row control circuit RC is initiated, and an active signal ACT is output (time t1). A bit line short signal BRS is deactivated by this signal ACT, and bit line precharge period terminates (time t1). In addition, a word line WL is selected by means of a word decoder WD, and memory cells Tc and Td are connected to the bit lines BL1 and BL2 (time t2). In this manner, the stored charge of the memory cells Tc and Td is started to be redistributed into the bit lines BL1 and BL2. FIG. 21 shows a case in which data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are written into the memory cells Tc and Td. Therefore, the bit line BL1 rises from a precharge voltage VPR, and conversely, the bit line BL2 falls.
In a process in which the stored charge from the memory cells Tc and Td selected by the word line WL is redistributed to each of the bit lines BL1 and BL2, a second internal command signal CMD is issued. This second command signal CMD is an internal command signal internally generated in the case where an external one command (not shown) is a write command. After this signal has been output, the column control circuit CC is initiated, and a control signal WR is output. In addition, a data bus short signal circuit DBSS deactivates a data bus short signal CPR, and terminates a precharge period of the data buses DB and /DB. In addition, this circuit activates a write amplifier WA by means of an activation signal WAE, and amplifies write data between data buses DB and /DB (time t3).
At a time t4 delayed from the time t3, the control signal WC output from the column control circuit CC works as trigger to make a switch signal CL1 output from a column switch signal circuit CS that corresponds to column address signals ADCn (n=1, 2, . . . ) active, and make column switches TN1 and TN2 conductive. As a result, the data buses DB and /DB and the bit lines BL1 and /BL1 are interconnected to each other, and the preceding write data amplified in the data buses DB and /DB are written into the bit lines BL1 and /BL1.
A potential difference between bit line pair BL1 and /BL1 is amplified by being driven by the write amplifier WA. On the other hand, the stored charge of the memory cell Td or the like is redistributed between the memory cell Td or the like and bit line BL2 or the like into the other bit line pair containing the adjacent bit line pair BL2 and /BL2. The bit line /BL2 or the like in which a memory cell is not selected is kept to be a precharge voltage VPR, and thus, a potential difference between the bit line pair BL2 and /BL2 gradually increases. Then, after this potential difference has reached the amplification sensitivity of the sense amplifier SAM, an activation signal LE is set to its logical level xe2x80x9chighxe2x80x9d by means of the sense amplifier signal circuit SC. As a result, the sense amplifier SAM is driven, and the bit line pair BL2 and /BL2 is amplified (time t5). At this time, a potential difference between the bit line pair BL2 and /BL2 is about some tens of mV. The memory cells Ta to Td are memory cells of such type comprising a capacitor element as a memory element, and storing a charge in this capacity element, thereby storing data. A memory cell of such type requires a so-called refresh operation for replenishing a stored charge periodically. Therefore, in a data write cycle as well, it is general to make a refresh operation in line with the memory cell Td in which no data writing is carried out, of the selected memory cells Tc and Td.
After amplification, a control signal WCD is output from the column control circuit CC at a proper timing, and the output signal is input to the column switch signal circuit CS. In this manner, a switch signal CL1 is deactivated, and an activation signal WAE of a write amplifier WA is deactivated (time t6). Concurrently, a data bus short signal CPR is activated, and the data buses DB and/DB are precharged. A third command signal is output at a predetermined timing by means of an internal command signal CMD, and a precharge signal PRE is outputted from the row control circuit RC. The word line WL and activation signal LE of sense amplifiers SA and SAM are deactivated by means of the precharge signal PRE, and a bit line short signal BRS is activated. In this manner, the bit lines BL1, /BL1, BL2, and /BL2 are precharged, and a write cycle terminates.
FIG. 22 shows parasitic capacities existing between bit lines. At the memory cell section 1000 in the semiconductor integrated circuit device, memory cells containing memory cells Tc, Td, and Te or the like are disposed with high integrity, and thus, the bit lines BL1, /BL1, BL2, /BL2, BL3, and /BL3 or the like connected to these memory cells Tc, Td, and Te or the like run in parallel with each other adjacently. Therefore, parasitic capacity Cb exists between bit line pair and between the adjacent bit lines.
The following description will be given with respect to an effect on noise in the case where a write operation is carried out in a memory cell Tc. In more detail, an effect of noise caused by a write operation for the adjacent bit line /BL2 due to an effect of the parasitic capacity Cb will be described with reference to FIG. 23. FIG. 23A shows a time chart of writing in a bit line pair between a selected bit line BL1 and a complementary bit line /BL1 to which a memory cell Tc into which data is to be written is connected. FIG. 23B shows a time chart of readout from a memory cell Td for a refresh operation carried out in line with the adjacent bit line pair BL2 and /BL2.
When a bit line short signal BRS is deactivated, and a word line WL is activated, the stored charge is started to be redistributed into each of the bit lines BL1 and BL2 from the selected memory cells Tc and Td. Here, data xe2x80x9c1xe2x80x9d is stored in the memory cell Tc, and thus, a potential of the bit line BL1 is started to rise. In addition, data xe2x80x9c0xe2x80x9d is stored in the memory cell Td, and thus, a potential of the bit line BL2 is started to fall. Next, a switch signal CL1 is activated, and column switches TN1 and TN2 are made conductive. Further, for the purpose of a write operation for the memory cell Tc, data buses DB and /DB, whose data for writing is amplified at a proper timing with activation of the word line WL and bit lines BL1 and /BL1 are connected. Here, because of xe2x80x9c0xe2x80x9d data writing, a potential of the bit line BL1 is inverted by means of a write amplifier (WA in FIG. 20), and is set to a low level side. At this stage, the adjacent bit line BL2 is in the way of redistributing the stored charge from the memory cell Td. Since a potential difference between the bit line pair BL2 and /BL2 does not reach amplification sensitivity of the sense amplifier SAM, the sense amplifier SAM is in an inactive state. That is, the bit lines BL2 and /BL2 are in a floating state.
The bit line BL1 set to the low level side and the bit line /BL2 in a floating state are adjacent, and the parasitic capacity Cb being a line parasitic capacity exists. Because of this, a voltage transition of the bit line BL1 is transmitted to be capacity coupled with the adjacent bit lines /BL2 as well. The voltage transition quantity of the adjacent bit line /BL2 is determined depending on the voltage transition quantity of the bit line BL1 caused by the amplification strength of the write amplifier WA, a potential difference between the adjacent bit line pair BL2 and /BL2, and a parasitic capacity Cb or the like. As a result, a potential difference between the adjacent bit line pair BL2 and /BL2 is reversed by means of an activation signal LE of the sense amplifier SAM, and is amplified, and readout of the stored charge may be reversed, which is problematic.
This write noise does not always occur only between the adjacent bit lines. The easiness of noise propagation or the like changes variously due to manufacturing factors such as layout position relationship between a memory cell and a bit line, difference in dielectric constant of interline oxide film, or thickness of a metal wired layer.
With advancement of higher integrity and higher speed of a semiconductor integrated circuit device, an effect of a write noise relevant to the adjacent bit lines is serious, which is problematic.
The present invention has been made in order to solve the foregoing problem with the prior art. It is an object of the present invention to provide a semiconductor integrated circuit device capable of, when a data writing operation for a memory cell is carried out by being embodied in a period during data readout from the memory cell for the adjacent bit lines, clamping a complementary bit line side of the adjacent bit line pair to a predetermined voltage, thereby reducing an effect of a write noise in a read operation for the adjacent bit lines, and making a constant operation.
In order to achieve the foregoing object, a semiconductor integrated circuit device according to one aspect of the present invention comprises a plurality of memory cells, a plurality of word lines, and a plurality of bit line pairs, and further comprises a voltage fixing section for fixing to a predetermined voltage at least one bit line excluding a predetermined bit line or at least one bit line excluding the complimentary bit line of the predetermined bit line when data is written into the predetermined bit line or a complementary bit line of the predetermined bit line.
In addition, a data writing method of a semiconductor integrated circuit device according to one aspect of the present invention, comprising: memory cells selected by a word line being activated; bit lines provided for each of the memory cells, and connected to the memory cells by selecting the word line, and complementary bit lines paired with the bit lines for amplifying data input from/output to the memory cell, the method comprising the voltage fixing step of, when data is written into a predetermined bit line or complementary bit line of the predetermined bit line, fixing to a predetermined voltage a plurality of complementary bit lines containing a complementary bit line of the predetermined bit line or a plurality of bit lines containing the predetermined bit line.
In the semiconductor integrated circuit device according to one aspect of the present invention, when data is written into a predetermined bit line or a complementary bit line of the predetermined bit line, a complementary bit line of the adjacent predetermined bit line to the predetermined bit line or a predetermined bit line adjacent to a complementary bit line of the predetermined bit line is set to a predetermined voltage by means of the voltage fixing section.
In this manner, a complementary bit line or a bit line that exist between the bit line or the complementary bit line to which a memory cell targeted for writing is connected and the adjacent bit lines or the adjacent complementary bit lines in which the stored charge is redistributed from a memory cell for the purpose of a refresh operation is fixed to a predetermined voltage. As a result, the capacity coupling caused by a voltage transition of a write bit line or write complementary bit line is shielded, thereby, a voltage transition can be prevented from being extended to the adjacent bit line or adjacent complementary bit line.
With advancement of a high integrity or high speed of a semiconductor integrated device, even if the parasitic capacity between the adjacent bit line and the complementary bit line or the adjacent complementary bit line and the bit line is increased, an effect caused by a write noise can be reliably prevented.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limit of the invention.